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DATE 2023 Awards

2023 EDAA Achievement Award

Jason Cong, UCLA, US

IEEE CEDA Service Award

Cristiana Bolchini, Politecnico di Milano, IT

ESDA / CEDA Phil Kaufman Award 2022:

Giovanni De Micheli, EPFL, CH

IEEE CS TTTC Outstanding Contribution Award

Ian O’Connor, École Centrale de Lyon, FR


Alessio Burrello, Politecnico di Torino and Università di Bologna, IT

            Optimizing Ai: From Network Topology Design To Mcu Deployment

Jatin Arora, CISTER Research Centre, ISEP, IPP, PT

            Shared Resource Contention Aware Schedulability Analysis For Multiprocessor Real-Time Systems

EDAA Outstanding Dissertations Award 2023

Topic 1:

Xiaochen Peng, Ph.D

Benchmark Framework for 2-D/3-D Integrated Compute-in-Memory based Machine Learning Accelerator

Topic 2:

Martin Rapp, Ph.D.

Machine Learning for Resource-Constrained Computing Systems

Topic 3:

Zhiyao Xie, Ph.D.

Intelligent Circuit Design and Implementation with Machine Learning

Topic 4:

Hasan Hassan, Ph.D.

Improving DRAM Performance, Reliability, and Security by Rigorously Understanding Intrinsic DRAM operations

DATE Fellow Award 2023

Cristiana Bolchini, Politecnico di Milano, IT

DATE 2023 also presented the DATE Fellow Awards from DATE 2020 to DATE 2022:

DATE 2020 Fellow Award: Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), DE

DATE 2021 Fellow Award: Giorgio di Natale, TIMA (CNRS), Grenoble, FR

DATE 2022 Fellow Award: Franco Fummi, University of Verona, IT

DATE Best Paper Awards 2023

Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs Lukas Sekanina, Alberto Bosio, Ilia Polian and Liliana Cucu and the following members: Katell Morin-Allory, Jeronimo Castrillon, Alessio Spessot, Julio Medina, Jean-Philippe Noel, Lorena Anghel, Dimitris Gizopoulos, Rosa Rodríguez-Montañés, Kazuo Sakiyama, Elke De Mulder, Ahmed Rezine, Cristiana Bolchini, Callie Cong, Julien Forget and Masanori Hashimoto.


Hardware Efficient Weight-Binarized Spiking Neural Networks

Chengcheng Tang and Jie Han

University of Alberta, CA


Automated Energy-Efficient DNN Compression under Fine-Grained Accuracy Constraints

Ourania Spantidi and Iraklis Anagnostopoulos

Southern Illinois University Carbondale, US


SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility

Haoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang and Ru Huang

Peking University, CN


PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation

Zhuoran Song, Heng Lu, Gang Li, Li Jiang, Naifeng Jing and Xiaoyao Liang

Shanghai Jiao Tong University, CN

Best Paper Award Nominations

D Track

Perspector: Benchmarking Benchmark Suites

Sandeep Kumar1; Abhisek Panda2; Smruti R. Sarangi1

1IIT Delhi, IN; 2Indian Institute of Technology, IN

A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN Accelerators

Yuanchen Qu; Yu Ma; Pingqiang Zhou

Shanghaitech University

GraphIte: Accelerating Iterative Graph Algorithms on ReRAM Architectures via Approximate Computing

Dwaipayan Choudhury; Ananth Kalyanaraman; Partha Pratim Pande

Washington State University 

Narrowing The Synthesis Gap: Academic FPGA Synthesis Is Catching Up With The Industry

 Benjamin Barze1; Arya Reais-Parsi1; Eddie Hung2; Minwoo Kang1; Alan Mishchenko1; Jonathan W. Greene1; John Wawrzynek1

1UC Berkeley, US; 2FPG-eh Research and University of British Columbia 

Computing Effective Resistances on Large Graphs Based on Approximate Inverse of Cholesky Factor

Zhiqiang Liu; Wenjian Yu

Tsinghua University

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach

Dewmini Marakkalage; Giovanni De Micheli 

Ecole Polytechnique Fdrale de Lausanne (EPFL)

Hardware Efficient Weight-Binarized Spiking Neural Networks 

Chengcheng; Jie Han

University of Alberta 

Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement

Wenlu Xue; Jinyu Bai; Sifan Sun; Wang Kang 

Beihang University

PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAM

Kailash Prasad; Aditya Biswas; Arpita Kabra; Joycee Mekie 

Indian Institute of Technology Gandhinagar

Benchmarking Large Language Models for Automated Verilog RTL Code Generation

Shailja Thakur1; Baleegh Ahmad1; Zhenxing Fan1; Hammond Pearce1; Benjamin Tan2; Ramesh Karri1; Brendan Dolan-Gavitt1; Siddharth Garg1 

1New York University; 2University of Calgary

Processor Verification using Symbolic Execution: A RISC-V Case Study

Niklas Bruns1; Vladimir Herdt2; Rolf Drechsler1,2 

1University of Bremen, 2DFKI

Synthesis with Explicit Dependencies

Priyanka Golia1,2; Subhajit Roy1; Kuldeep S Meel2

1IIT Kanpur, 2National University of Singapore

Minimizing Communication Conflicts in Network-On-Chip based Processing-In-Memory Architecture

Hanbo Sun; Tongxin Xie; Zhenhua Zhu; Guohao Dai; Huazhong Yang; Yu Wang

Tsinghua University

 Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware Caches

Shiqing Li; Weichen Liu 

Nanyang Technological University

PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLows

Yuhan Chen; Alireza Khadem; Xin He; Nishil Talati; Tanvir Ahmed Khan; Trevor Mudge

University of Michigan

SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility

Haoyi Zhang; Xiaohan Gao; Haoyang Luo; Jiahao Song; Xiyuan Tang; Junhua Liu; Yibo Lin; Runsheng Wang; Ru Huang

Peking University

Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREP

Sayandeep Saha; Prasanna Ravi; Dirmanto Jap; Shivam Bhasin

Nanyang Technological University, Singapore

Efficient Software Masking of AES through Instruction Set Extensions

Songqiao Cui; Josep Balasch

KU Leuven

Hardware Trojans in eNVM Neuromorphic Devices

Lingxi Wu; Rahul Sreekumar; Rasool Sharifi; Kevin Skadron; Stan Mircea; Ashish Venkat 

University of Virginia

SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing

Muhammad Monir Hossain; Arash Vafaei; Kimia Zamiri Azar; Fahim Rahman; Farimah Farahmandi; Mark Tehranipoor 

University of Florida

A Track

Automated Energy-Efficient DNN Compression under Fine-Grain Accuracy Constraints

Ourania Spantidi; Iraklis Anagnostopoulos 

Southern Illinois University Carbondale

Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Manycore Processor

Marco Bertuletti1; Yichao Zhang1; Alessandro Vanelli-Coralli1,2; Luca Benini1,2

1ETH Zurich; 2Universita di Bologna

EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction

Rui Guo; Mohammad Rahman; Hadi Mardani Kamali; Fahim Rahman; Farimah Farahmandi;

Mark Tehranipoor University of Florida

RTLock: IP Protection using Scan-Aware Logic Locking at RTL

Md Rafid Muttaki; Shuvagata Saha; Hadi Mardani Kamali; Fahim Rahman; Mark Tehranipoor;

Farimah Farahmandi

University of Florida

CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and Compensation

Amro Eldebiky1; Grace Li Zhang2; Georg Bocherer3; Bing Li1; Ulf Schlichtmann1

1Technical University of Munich; 2TU Darmstadt; 3Huawei Munich Research Center

T Track

Device-Aware Test for Back-Hopping Defects in STT-MRAMs

 Sicong Yuan1; Mottaqiallah Taouil1; Moritz Fieback1; Hanzhi Xun1; Erik Jan Marinissen2; Gouri Kar2; Siddharth Rao2; Sebastien Couet2; Said Hamdioui1

1Delft University of Technology; 2IMEC

Assessing Convolutional Neural Networks Reliability through Statistical Fault Injections

Annachiara Ruospo1; Gabrile Gavarini1; Corrado De Sio1; Juan Guerrero Balaguera1; Luca Sterpone1; Matteo Sonza Reorda1; Ernesto Sanchez1; Riccardo Mariani2; Joseph Aribido2;

Jyotika Athavale2 1Politecnico di Torino; 2NVIDIA

E Track

Light Flash Write for Efficient Firmware Update on Energyharvesting IoT Devices

Songran Liu1; Mingsong Lv2; Wei Zhang3; Xu Jiang1; Chuancai Gu4; Tao Yang4; Wang Yi5; Nan Guan6

1Northeastern University; 2The Hong Kong Polytechnic University; 3Shandong University; 4Huawei Technologies Company; 5Uppsala University; 6City University of Hong Kong

Ditty: Directory-based Cache Coherence for Multicore Safety-critical Systems

Zhuanhao Wu; Marat Bekmyrza; Nachiket Kapre; Hiren Patel

University of Waterloo

PRADA: Point Cloud Recognition Acceleration via Dynamic Approximation 

Zhuoran Song; Heng Lu; Gang Li; Li Jiang; Naifeng Jing; Xiaoyao Liang

Shanghai Jiao Tong University 

Federated Learning with Heterogeneous Models for On-device Malware Detection in IoT Networks

Sanket Shukla1; Setareh Rafatirad2; Houman Homayoun2; Sai Manoj Pudukotai Dinakarrao1 1George Mason University; 2University of California Davis

Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core Systems

Sebastian Karl1; Arne Symons2; Nael Fasfous; Marian Verhelst2

1TU Munich; 2KU Leuven; 3BMW AG

HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance Scaling

Halima Bouzidi1; Mohanad Odema2; Hamza Ouarnoughi3; Mohammad Al Faruque2;  Smail Niar3

1Univ. Polytechnique Hauts-de-France, LAMIH; 2University of California Irvine; 3INSA Hautsde-France

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