Technology scaling has enabled fast advancement of computing architectures through high-density integration of components and cores, and the provision of powerful systems on chip (SoC), e.g. NVIDIA Jetson, AMD/Xilinx UltraScale+ FPGA, ARM big.LITTLE. However, such systems are becoming hot and more prone to failure and timing violations as clock speed limits are reached. Therefore, parts of SoCs must be turned off to stay within thermal limits ("dark silicon"). This shifts challenges away from making designs smaller, setting the new focus on systems that are ultra-low power, resilient and autonomous in their adaptation to anomalies, faults, timing violations and performance degradation. There is a significant increase in numbers of temporary faults caused by radiation, and permanent faults due to manufacturing defects and stress. ITRS (https://irds.ieee.org/) estimates significant device failure rates, e.g., due to wear-out, in the short term. Hence, a critical requirement for such systems is to effectively perform detection and analysis at runtime, within a minimal area and power overhead. This is at odds with current state-of-the-art, including error correcting codes (ECC), built-in-self-test (BIST), localized fault detection, and traditional modular redundancy strategies (TMR), all resulting in prohibitively high system overheads and an inability to adapt, locate or predict faults. At the same time, technology diversification (More than Moore) is making fast progress, delivering technologies such as, e.g., memristors, graphene nanowires, etc. The current major issue of these technologies is large device variability preventing efficient scalability and usability. In this case, there are not even systematic state-of-the-art error correction or fault control strategies available yet.

This Nervous System on Chip tutorial is therefore discussing bio-inspired solutions becoming viable with the neuromorphic hardware design concepts becoming more mature. We will briefly introduce the principles of spiking neural networks, biological nervous systems, unconventional computing, and how to translate key concepts into functional hardware systems. We will primarily focus on SNNs for fault-tolerance, nervous system sense/act pathways, and multi-objective novelty search as an artificial nervous systems design methodology. Case studies will include an efficient SNN-based approach to detect timing violations in digital hardware, consider how efficient neuromorphic hardware may be achieved using a reservoir computing model, and highlight the challenges ahead. There will be some opportunity to run, for example, SNN, reservoir computing, or novelty search examples in simulation during a hands-on session.