With the rise of open-source hardware and the never-ending requirements for computational power for modern applications, companies are increasingly interested in investments to create novel chips. However, these investments can be undermined by malicious actors in the semiconductor supply chain that can reverse engineer the chip design, steal hardware intellectual property, and make authorized copies of the original design. So, protecting the hardware intellectual property is becoming a critical concern to protect the huge investments behind developing novel architectures. 

FPGA redaction is a novel, promising technique that aims to thwart reverse engineering attacks on integrated circuits (IC) by exploiting the flexibility of reconfigurable devices. Critical IC parts are mapped on and replaced by specific reconfigurable blocks (called embedded FPGAs - eFPGAs) with a two-fold goal: (1) during fabrication, reconfigurable devices can implement any arbitrary functions, without revealing their intended functionality; (2) during execution, they can be configured to implement the correct functionality by classic FPGA programming methods. In this context, novel tools like OpenFPGA can automate and significantly accelerate the development cycle of customizable FPGA architectures. Such tools can generate Verilog netlists associated with such customized FPGA that can be directly used to generate production-ready layouts.

This tutorial presents ALICE, a design flow that leverages OpenFPGA to explore a chip design (described at the behavioral register-transfer level), identify the best modules for redaction, and create the corresponding eFPGAs. This framework automates the process of eFPGA redaction, enabling its use in industrial environments.