The wide adoption of data-intensive algorithms to tackle today’s computational problems introduces new challenges in designing efficient computing systems to support these applications. In critical domains such as machine learning and graph processing, data movement remains a major performance and energy bottleneck. As repeated memory accesses to off-chip DRAM impose an overwhelming energy cost, we need to rethink the way embedded (i.e., on-chip) memory systems are built in order to increase storage density and energy efficiency beyond what is currently possible with SRAM. To address these challenges and empower future memory system design, we developed NVMExplorer: a design space exploration framework that addresses key cross-computing-stack design questions and reveals opportunities and optimizations for embedded NVMs under realistic system-level constraints, while providing a flexible interface and modular evaluation to empower further investigations.

This tutorial will describe and walk through hands-on design studies using our open-source code base (NVMExplorer, http://nvmexplorer.seas.harvard.edu/), highlighting the most up-to-date features of our suite of tools including integration with additional memory

characterization tools and system simulator results. We will also guide attendees to configure their own design studies based on research interests.

At the end of this tutorial, attendees will be able to use NVMExplorer to evaluate and compare the application-level power and performance impact of a variety of eNVM solutions, including different technology configurations, varying system settings and optimization targets, and a range of application memory traffic patterns.