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M06 Design, Programming, and Partial Reconfiguration of Heterogeneous SoCs with ESP

Start
Wednesday, 19 April 2023 11:00
End
Wednesday, 19 April 2023 12:30
Room
Toucan Room 2.7.1/2
Organiser
Luca Carloni, Columbia University , United States
Organiser
Joseph H. Zuckerman, Columbia University in the City of New York, United States

Energy-efficient, high-performance computing requires the integration of specialized accelerators with general-purpose processors. Designing such systems, however, imposes a difficult set of challenges: integrating many components of different natures into a single SoC; designing new components targeting a particular application domain with a limited team size; dealing with ever-changing software; accelerating multiple applications with a fixed area and power budget. In this tutorial, we present ESP, an open-source platform to support research on the design and programming of heterogeneous SoC architectures. By combining a scalable, modular tile-based architecture with a flexible system-level design methodology, ESP simplifies the design of individual accelerators and automates their hardware/software integration into complete SoCs. In particular, we demonstrate several capabilities of ESP to meet the challenges described above. First, we show how to use the commercial Catapult HLS tool and the open-source Matchlib library to design an accelerator in SystemC; this is a new example of one of the design flows supported by the ESP methodology that simultaneously raise the level of abstraction in the design process and allow designers to conduct a broader design-space exploration. Next, we demonstrate how ESP simplifies the integration of the accelerator into a complete SoC and enables its functional and performance evaluation through rapid FPGA-based prototyping. Finally, we show how recent advances in ESP make it possible to reduce the amount of dark silicon in SOC architectures through fine-grained partial reconfiguration of accelerator tiles.

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