Abstract: Silicon implementations of complex algorithms (for communications and other applications) are burdened by extensive  savety margins to ensure 100% reliable operation. These margins limit voltage scaling at the cost of energy/power consumption and require conservative layout rules such as double-fins or the use of static memories for storage that are costly in area. "Approximate computing" or "computing on unreliable silicon" promotes the idea to compromise reliability and tolerate occasional errors or parameter variations for the benefit of area and power/energy. This idea is especially relevant for applications such as communications or machine learning, where systems are anyway tolerant to noise or apply only stochastic quality metrics such as BER, FER, PSNR, or MSE.
Unfortunately, the silicon industry has so far refused to even remotely consider any idea that involves compromising 100% reliable operation.
The good reason for this strict conservative, but costly (in area and power) approach is that the nature of errors (e.g., due to variations in the manufacturing process) are highly unpredictable and that it is almost impossible to predict the impact of a small error in the silicon on quality of results (e.g., on the error rate in a communication receiver). In fact, reliability issues lead to a huge quality spread between manufactured chips even for the most fault tolerant applications. However, chip manufacturers must provide reliable quality guarantees to their customers. While for example a slightly degraded, but consistent error rate performance or image quality is perfectly acceptable, it is not acceptable if some  circuits provide good quality, while others provide only poor quality.
The key to successfully exploit quality margins for the benefit of area and power is therefore not necessarily to minimize errors, but to ensure that all manufactured chips provide the same quality level, even if they are subject to different more or less random errors.
In this talk, we will explain this issue in detail by analyzing the nature of those errors that approximate computing promotes to tolerate. We argue that the randomness of errors is not only a curse, but can also be a beautiful characteristic that enables reliable quality guarantees. However, this beauty is not always naturally present in the silicon manufacturing process, but it can be restored. We will illustrate this with different examples, including an embedded system with a voltage-over-scaled SRAM and with the first silicon implementation of an LDPC decoder that overcomes the limitations of an unreliable memory.

Bio: Andreas Burg (S'97-M'05) was born in Munich, Germany, in 1975. He received his Dipl.-Ing. degree from the Swiss Federal Institute of Technology (ETH) Zurich, Switzerland, in 2000, and the Dr. sc. techn. degree from the Integrated Systems Laboratory of ETH Zurich, in 2006.
In 1998, he worked at Siemens Semiconductors, San Jose, CA. During his doctoral studies, he worked at Bell Labs Wireless Research for a total of one year. From 2006 to 2007, he was a postdoctoral researcher at the Integrated Systems Laboratory and at the Communication Theory Group of the ETH Zurich. In 2007 he co-founded Celestrius, an ETH-spinoff in the field of MIMO wireless communication, where he was responsible for the ASIC development as Director for VLSI. In January 2009, he joined ETH Zurich as SNF Assistant Professor and as head of the Signal Processing Circuits and Systems group at the Integrated Systems Laboratory. In January 2011, he joined the Ecole Polytechnique Federale de Lausanne (EPFL) where he is leading the Telecommunications Circuits Laboratory. He was promoted to Associate Professor with Tenure in June 2018.
Mr. Burg has served on the TPC of various conferences on signal processing, communications, and VLSI. He was a TPC co-chair for VLSI-SoC 2012 and the TCP co-chair for ESSCIRC 2016 and SiPS 2017. He was a General Chair of ISLPED 2019 and he served as an Editor for the IEEE Transaction of Circuits and Systems in 2013 and on the Editorial board of the Springer Microelectronics Journal. He is currently an editor of the Springer Journal on Signal Processing Systems, the MDPI Journal on Low Power Electronics and its Applications, the IEEE Transactions on VLSI, and the IEEE Transactions on Signal Processing. He is also a member of the EURASIP SAT SPCN and the IEEE CAS-VSATC.