Abstract: As the great success of artificial intelligence algorithms, machine learning SoC are becoming a significant type of high performance processors recently. However, the limited power budget of edge devices cannot support GPUs and intensive DRAM access. The talk will discuss multiple energy efficient codesign examples to avoid power hungry hardware. First, on-chip incremental learning is performed on an SoC without dedicated backpropagation computing, where algorithm-architecture codesign is involved. Second, low bit-width quantization schemes are applied to computing-in-memory based SoC, where algorithm-circuit codesign is investigated. Moreover, data flow optimization is mapped onto a multi-chiplet-module system, where architecture-package codesign is discussed.