Abstract: A distributed massive MIMO channel sounder for acquiring CSI datasets is presented. The measured data has several applications in the study of different machine learning algorithms. Each individual single-antenna receiver is completely autonomous, enabling arbitrary grouping into spatially distributed antenna deployments, and offering virtually unlimited scalability in the number of antennas. Some of the deep learning applications presented include absolute and relative user localization like “channel charting”, and CSI inference for UL/DL FDD massive MIMO operation.

Bio: Stephan ten Brink has been a faculty member at the University of Stuttgart, Germany, since July 2013, where he is head of the Institute of Telecommunications. From 1995 to 1997 and 2000 to 2003, Dr. ten Brink was with Bell Laboratories in Holmdel, New Jersey, conducting research on multiple antenna systems. From July 2003 to March 2010, he was with Realtek Semiconductor Corp., Irvine, California, as Director of the wireless ASIC department, developing WLAN and UWB single chip MAC/PHY CMOS solutions. In April 2010 he returned to Bell Laboratories as Department Head of the Wireless Physical Layer Research Department in Stuttgart, Germany. Dr. ten Brink is an IEEE Fellow, and recipient and co-recipient of several awards, including the Vodafone Innovation Award, the IEEE Stephen O. Rice Paper Prize, and the IEEE Communications Society Leonard G. Abraham Prize for contributions to channel coding and signal detection for multiple-antenna systems. He is best known for his work on iterative decoding (EXIT charts), MIMO communications (soft sphere detection, massive MIMO), and deep learning applied to communications.

Abstract: As the great success of artificial intelligence algorithms, machine learning SoC are becoming a significant type of high performance processors recently. However, the limited power budget of edge devices cannot support GPUs and intensive DRAM access. The talk will discuss multiple energy efficient codesign examples to avoid power hungry hardware. First, on-chip incremental learning is performed on an SoC without dedicated backpropagation computing, where algorithm-architecture codesign is involved. Second, low bit-width quantization schemes are applied to computing-in-memory based SoC, where algorithm-circuit codesign is investigated. Moreover, data flow optimization is mapped onto a multi-chiplet-module system, where architecture-package codesign is discussed.