Sparse linear algebra operations are widely used in numerous application domains such as graph processing, machine learning, and scientific computing. These operations are typically more challenging to accelerate due to low operational intensity and irregular data access patterns.

This talk presents our recent investigation into near-memory hardware acceleration for sparse processing. Specifically, I will discuss the importance of co-designing the sparse storage format and  accelerator architecture to maximize the bandwidth utilization and compute occupancy. As a case study, I will introduce GraphLily, a graph linear algebra overlay for accelerating graph processing on HBM-equipped FPGAs. GraphLily supports a rich set of graph algorithms by adopting the GraphBLAS programming interface, which formulates graph algorithms as sparse linear algebra operations.